PIC16C54C-04/SO【PDF 174/194 页】IC MCU OTP 512X12 18SOIC

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Sheet目录3886

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PIC18F2450/4450

DS39760A-page 78

Advance Information

2006 Microchip Technology Inc.

6.4

Erasing Flash Program Memory

The minimum erase block is 32 words or 64 bytes. Only

through the use of an external programmer, or through

ICSP control, can larger blocks of program memory be

Bulk Erased. Word Erase in the Flash array is not

supported.

When

initiating

erase

sequence

from

the

microcontroller itself, a block of 64 bytes of program

memory is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.

The WREN bit must be set to enable write operations.

The FREE bit is set to select an erase operation.

For protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

6.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory is:

Load Table Pointer register with address of row

being erased.

Set the EECON1 register for the erase operation:

clear the CFGS bit to access program memory;

set WREN bit to enable writes;

set FREE bit to enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write 0AAh to EECON2.

Set the WR bit. This will begin the Row Erase

cycle.

The CPU will stall for duration of the erase

(about 2 ms using internal timer).

Re-enable interrupts.

EXAMPLE 6-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

ERASE_ROW

BCF

EECON1, CFGS

; access Flash program memory

BSF

EECON1, WREN

; enable write to memory

BSF

EECON1, FREE

; enable Row Erase operation

BCF

INTCON, GIE

; disable interrupts

Required

MOVLW

55h

Sequence

MOVWF

EECON2

; write 55h

MOVLW

0AAh

MOVWF

EECON2

; write 0AAh

BSF

EECON1, WR

; start erase (CPU stall)

BSF

INTCON, GIE

; re-enable interrupts

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